Heretofore, in memory devices, especially DRAMs (dynamic random access memories) and logic chips having embedded DRAMs (eDRAMs), the process of fabricating bitline contacts to diffusion (CB contacts) has required lithography using a critical mask. Fabricating the bitlines themselves has required lithography using another critical mask. Critical mask lithography is expensive and error-prone due to attendant optical and alignment factors. Therefore, it would be desirable to simultaneously fabricate bitlines and bitline contacts to diffusion using the same critical mask. In the description of the invention that follows, those skilled in the art will recognize that bitlines are a specific example of a line interconnect, and bitline contacts are a specific example of contacts to diffusion.
Many semiconductor chips have array regions and support regions. The array regions may include densely packed devices that form a memory array for a DRAM or an eDRAM, while the support regions include less densely packed devices, typically logic, which may be optimized for speed, performance or power conservation. The different design goals for the array region and the support region require that different processing be applied to the respective regions. However, to reduce the cost of manufacturing such chips, it is desirable to combine the processing for both the array and the support regions, when certain steps can be performed which advance the design goals for both regions.
Accordingly, it is an object of the invention to provide a method of simultaneously defining line interconnects, e.g. bitlines, and contacts to diffusion, e.g. bitline contacts.
Another object of the invention is to provide a method of defining line interconnects and contacts to diffusion while requiring only one critical mask.
Still another object of the invention is to provide a method of simultaneously defining line interconnects, e.g. bitlines, array contacts to diffusion, e.g. bitline contacts, and support contacts to diffusion.